1. Field of the Invention
The present invention relates to a semiconductor memory device, a method for manufacturing the same, a memory circuit, and a method for driving the same, and more particularly, to a single transistor cell, a method for manufacturing the same, a memory circuit composed of the single transistor cells, and a method for driving the memory circuit.
2. Description of the Related Art
A ferroelectric material is a dielectric material in which polarization generated by an external electric field remains partially after removing the external electric field, and the polarization direction can be changed by changing the direction of the external electric field.
Memory devices manufactured using a ferroelectric thin film may be categorized into two types.
The first type of device is a destructive read out (DRO) type memory device, which means that when data is read out, the data is lost from the memory and must be written again. The device is constituted with a capacitor which is manufactured using a ferroelectric thin film dielectric, and a transistor which is used to read or write signals of two directions stored in the capacitor. Here, the memory device is commonly called a ferroelectric random access memory (FRAM), and the driving principle thereof is similar to a dynamic random access memory (DRAM). However, unlike the DRAM, the FRAM requires no refresh and is a non-volatile memory which keeps stored information even when the power supply is turned off.
The second type of device is a non-destructive read out (NDRO) ferroelectric memory device which reads stored information without destruction, unlike the DRO memory device. The device is obtained by forming a ferroelectric capacitor on the gate electrode of a transistor, and operates by determining whether a channel exists in a silicon surface under a gate oxide layer along a polarization direction of the ferroelectric capacitor. For instance, it is recognized that if a channel exists, 1 is written, and if not, 0 is written.
A memory cell including only a single transistor without a capacitor, unlike the DRAM or FRAM, would be advantageous for integration, but would require an access for selecting a cell or a selection transistor in order to perform random access.
No method for exactly realizing an array of cells each formed of only one transistor of an NDRO type has been disclosed. However, a similar SFRAM is disclosed in U.S. Pat. No. 5,070,385 "Ferroelectric non-volatile variable resistive element" by Evans, Jr., Joseph T. and Bullington, Jeff A.
FIG. 1 is a sectional view of a conventional SFRAM, disclosed in the above patent.
In FIG. 1, reference numeral 10 indicates a gate, which is actually part of, a word line, reference numeral 12 indicates a ferroelectric layer, reference numeral 14 indicates a channel region, reference numeral 16 indicates a drain, reference numeral 18 indicates a source, reference numeral 20 indicates an interdielectric layer, reference numeral 22 indicates a first metal electrode, and reference numeral 24 indicates a second metal electrode.
The SFRAM of FIG. 1 is a thin film transistor (TFT). The word line 10 is formed on a semiconductor substrate (not shown), and the ferroelectric layer 12 is formed on the word line 10. Here, an oxide layer (not shown) is interposed between the word line 10 and the semiconductor substrate. The drain 16 is formed on a left semiconductor layer around the word line 10, and the source 18 is formed on the right semiconductor layer. The channel region 14 is formed between the drain 16 and the source 18 above the word line 10.
When a predetermined voltage is applied to the word line 10, the spontaneous polarization is induced in the ferroelectric layer 12, and thus a conductive channel is formed or not formed in the channel region 14.
For instance, if the source and drain are doped with an N-type impurity, and by a drive method "1" or "0" is written to a cell transistor, then "1" indicates the state in which the conductive channel is formed in the channel region, and "0" indicates the in which no conductive channel is formed. When a positive voltage (+V) is applied to the word line 10, N-type ions are accumulated in the channel region 14 due to the polarization of the ferroelectric layer 12, so that the conductive channel is formed, to thereby write "1" in the cell transistor. When a negative voltage (-V) is applied to the word line 10, P-type ions are accumulated in the channel region 14 due to the polarization of the ferro dielectric layer 12, so that a non-conductive channel is formed, to thereby write "0" in the cell transistor.
Meanwhile, in order to read the data stored in the cell transistor, if +V is applied to the second metal electrode 24 while the conductive channel is formed in the channel region 14, i.e., "1" is written, current passes through the first metal electrode 22, and if a non-conductive channel is formed in the channel region 14, i.e., "0" is written, current does not pass through the first metal electrode 22. Thus, the current passing through the first metal electrode 22 is measured, to thereby read the cell transistor of "1" or "0".
In the conventional SFRAM, read and write are performed by normal drive of the unit cell. However, in order to read or write information in an arbitrary unit cell, each cell requires a further two access transistors, which prevents high integration density for the memory device.